Conference Papers

2025

LISA: LLM-Informed SystemVerilog Assertion Generation
Subhajit Paul, Ansuman Banerjee, Sumana Ghosh
Accepted at IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025)
Indian Statistical Institute, Kolkata

Abstract: This paper presents a novel framework that leverages Large Language Models to automatically generate SystemVerilog assertions, supporting reliable RTL development and enhancing verification workflows in Electronic Design Automation.

LLM-Guided Reconciliation for Explainable Robotic Path Planning
Subhajit Paul, Ansuman Banerjee
Accepted at IEEE Autonomic Computing and Self-Organizing Systems (ACSOS 2025)
Indian Statistical Institute, Kolkata
Status: To Appear

Abstract: This work explores the application of Large Language Models in model reconciliation for robotic path planning, providing explainable solutions for autonomous navigation systems.

Research Interests

My research focuses on developing innovative frameworks that bridge Formal Verification and Generative Artificial Intelligence. Key areas include:

• SystemVerilog Assertion Generation using Large Language Models
• Model Reconciliation for explainable robotic systems
• Agentic Workflows in Electronic Design Automation
• Verification Environment Generation through AI-driven approaches

Ongoing Research

Currently working on expanding the application of agentic workflows in EDA for automated verification environment generation at the Indian Statistical Institute, Kolkata.

Collaboration & Contact

I’m always interested in collaborating on research projects involving:

• Formal verification methodologies
• AI applications in electronic design automation
• Large language models for hardware verification
• Explainable AI in robotics

Contact: test.dev.paul@gmail.com